MOSI
  • Master Data Output, Slave Data Input
MISO
  • Master data input, Slave data output
SCLK
  • Clock signal, generated by the master device, up to fPCLK/2, slave mode frequency up to fCPU/2
SS/CSS
  • Slave enabled signal, controlled by the master device, some ICs will be labelled as CS (Chip select)
SDA
  • Serial Data Line
  • Transmit communication data
SCL
  • Serial Clock Line
  • Transmit CLK signals, generally provided by the master device to the slave device
SPI
UART
I2C